This application claims the priority of application Ser. No. 2001-361961, filed Nov. 28, 2001 in Japan, the subject matter of which is incorporated herein by reference.
The present invention relates generally to a semiconductor integrated circuit including a PLL (Phase Locked Loop) circuit therein. More particularly, the present invention relates to a method of jitter measurement of a PLL circuit contained in a semiconductor integrated circuit.
A conventional IC includes a PLL circuit, an external clock terminal, buffer circuits, a test terminal and a logic circuit. The logic circuit is provided with input terminals and output terminals. The PLL circuit generates master clocks based on the external clocks. The logic circuit performs a predetermined logical operation to an input signal, supplied to the input terminals, in synchronization with the master clock signals. Results of the logical operation by the logic circuit are outputted from the output terminals.
When a test is performed to the PLL circuit, an external logic analyzer is connected to the clock terminal and the test output terminal. In test, external clocks are supplied to the clock terminal, and output clocks supplied from the test terminal are used to detect or measure the frequency and jitter of the master clock signal. In accordance with such detection results, the PLL circuit is determined whether it has required characteristics.
xe2x80x9cJitterxe2x80x9d is abrupt or spurious variations in the phase of the frequency modulation of successive pulse reference to the phase of a continuous oscillator.
According to the above-described semiconductor IC, however, detected waveforms may become dull due to an impedance of a cable connected to the terminals and to the external analyzer. As a result, it is difficult to detect or measure the frequency and jitter of the PLL circuit reliably.
Accordingly, it is an object of the present invention to provide a semiconductor device in which the frequency and jitter of a PLL can be analyzed reliably.
Additional objects, advantages and novel features of the present invention will be set forth in part in the description that follows, and in part will become apparent to those skilled in the art upon examination of the following or may be learned by practice of the invention. The objects and advantages of the invention may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.
According to a first aspect of the present invention, a semiconductor device, includes a clock input terminal to which external clocks are supplied; a PLL circuit, which is supplied with the external clocks and generate first internal clocks; a logic circuit, which operates in synchronization with the internal clocks; and an internal counter, which counts the first internal clocks when the PLL circuit is tested. The internal counter is provided with an output terminal from which an output signal thereof is supplied to an external circuit.
According to a second aspect of the present invention, a semiconductor device, includes a clock input terminal to which external clocks are supplied; a PLL circuit, which is supplied with the external clocks and generate first internal clocks; a logic circuit, which operates in synchronization with the internal clocks; a test clock terminal to which test clocks are supplied from an external circuit, the test clock having a frequency with a predetermined phase difference from the external clocks; a flip-flop circuit, which is supplied with the test clocks and the first internal clocks to generate second internal clocks; and an internal counter, which counts the second internal clocks when the PLL circuit is tested. The internal counter is provided with an output terminal from which an output signal thereof is supplied to an external circuit.
According to a third aspect of the present invention, a semiconductor device, includes a clock input terminal to which external clocks are supplied; a PLL circuit, which is supplied with the external clocks and generate first internal clocks; a logic circuit, which operates in synchronization with the internal clocks; a test clock terminal to which test clocks are supplied from an external circuit, the test clock having a frequency with a predetermined phase difference from the external clocks; a flip-flop circuit, which is supplied with the test clocks and the first internal clocks to generate second internal clocks; an internal counter, which counts the second internal clocks when the PLL circuit is tested; and a selector, which selectively transfer one of the first clocks and the second clocks to the counter. The internal counter is provided with an output terminal from which an output signal thereof is supplied to an external circuit.